The invention relates to the field of extended silicide and external contact technology.
As computer usage grows, the demand for memory increases proportionately with ever increasing size of programs. The expense of large numbers of memory chips to implement a good size working memory however creates a bias toward implementing ever more memory cells on a single die. This decreases the package count, increases the reliability and decreases cost. If the same number of memory cells can be fit on a smaller die, the yield for that die will increase. Further, if more memory cells can be fit on the same size die then the yield for that die should be substantially the same, but the cost per bit will be less. Consequently there has developed a trend to try mightily to decrease the size of a single memory cell in its linear dimensions and area such that denser memory arrays can be fabricated at a lower cost per bit of storage.
Another major factor in the trend toward smaller memory cells is operating speed. Operating speed depends heavily upon the amount of capacitance coupled to various nodes in the circuit. Capacitance can arise from one conductor crossing over another, and from the transition and depletion capacitances associated with PN junctions. Since capacitance is directly related to the area of the capacitor, there will be a corresponding decrease in junction capacitances associated with transistors if the size of the transistor is decreased. The result is higher operating speed.
One of the factors in determining cells size and transistor size is the presence or absence of contacts to various nodes in the circuit and to the source and drain nodes of MOS transistors and to the emitter, base and collector nodes of bipolar transistors. Contacts often involve contact windows etched down through intervening insulation areas to the node of interest. Thereafter, metal is deposited over the chip such that it is deposited into the contact window and makes contact with the node of interest.
The difficulty with this is that a contact window cannot be made smaller than the minimum photolithographically obtainable dimension. In addition, to insure that the contact window hits its target given the vagaries of the alignment process during fabrication, it is necessary to make the target larger such that it overlaps the dimensions of the contact window to account for alignment tolerances and errors of alignment by fab operators. Accordingly, a need has arisen for a smaller transistor structure and a way of making very small transistors which can be used to make smaller and faster memory cells of both the static and dynamic variety. Further, there has arisen a need to devise a cell which minimizes the number of external contacts and thereby minimizes the number of contact window inside the perimeter of the cell to minimize the area consumed by the cell.